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The vector stencils library "Logic gate diagram" contains 17 element symbols for drawing the logic gate diagrams.
"To build a functionally complete logic system, relays, valves (vacuum tubes), or transistors can be used. The simplest family of logic gates using bipolar transistors is called resistor-transistor logic (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early integrated circuits. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in diode-transistor logic (DTL). Transistor-transistor logic (TTL) then supplanted DTL. As integrated circuits became more complex, bipolar transistors were replaced with smaller field-effect transistors (MOSFETs); see PMOS and NMOS. To reduce power consumption still further, most contemporary chip implementations of digital systems now use CMOS logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation." [Logic gate. Wikipedia]
The symbols example "Design elements - Logic gate diagram" was drawn using the ConceptDraw PRO diagramming and vector drawing software extended with the Electrical Engineering solution from the Engineering area of ConceptDraw Solution Park.
Logic gate symbols
Logic gate symbols, operational amplifier, gate, open-collector output, gate, Schmitt trigger input, buffer, OR gate, Norton opamp, Norton operational amplifier, NOT gate, inverter, NOR gate, NOT OR, NAND gate, NOT AND, EX-OR gate, exclusive-OR gate, EX-NOR gate, exclusive-NOR gate, AND gate,
HelpDesk

How to Create a Fault Tree Analysis Diagram (FTD) in ConceptDraw PRO

Fault Tree Diagram are logic diagram that shows the state of an entire system in a relationship of the conditions of its elements. Fault Tree Diagram are used to analyze the probability of functional system failures and safety accidents. ConceptDraw PRO allows you to create professional Fault Tree Diagrams using the basic FTD symbols. An FTD visualize a model of the processes within a system that can lead to the unlikely event. A fault tree diagrams are created using standard logic symbols . The basic elements in a fault tree diagram are gates and events.
The vector stencils library "Fault tree analysis diagrams" contains 12 symbols for drawing FTA diagrams in the ConceptDraw PRO diagramming and vector drawing software extended with the Fault Tree Analysis Diagrams solution from the Engineering area of ConceptDraw Solution Park.
www.conceptdraw.com/ solution-park/ engineering-fault-tree-analysis-diagrams
AND gate
AND gate, AND gate,
Priority AND gate
Priority AND gate, priority AND gate,
OR gate
OR gate, OR gate,
Inhibit gate
Inhibit gate, inhibit gate,
XOR gate
XOR gate, exclusive OR gate,
Event
Event, event,
Basic event
Basic event, basic event, basic initiating fault, failure event,
Undeveloped event
Undeveloped event, undeveloped event,
House event
House event, house event,
Conditional event
Conditional event, conditional event,
Transfer symbol
Transfer symbol, transfer,
Voting gate
Voting gate, voting gate,
The vector stencils library "Fault tree analysis diagrams" contains 12 symbols for drawing Fault Tree Analysis (FTA) diagrams.
"Fault tree analysis (FTA) is a top down, deductive failure analysis in which an undesired state of a system is analyzed using Boolean logic to combine a series of lower-level events. This analysis method is mainly used in the fields of safety engineering and reliability engineering to understand how systems can fail, to identify the best ways to reduce risk or to determine (or get a feeling for) event rates of a safety accident or a particular system level (functional) failure. FTA is used in the aerospace, nuclear power, chemical and process, pharmaceutical, petrochemical and other high-hazard industries; but is also used in fields as diverse as risk factor identification relating to social service system failure.
In aerospace, the more general term "system Failure Condition" is used for the "undesired state" / Top event of the fault tree. These conditions are classified by the severity of their effects. The most severe conditions require the most extensive fault tree analysis. These "system Failure Conditions" and their classification are often previously determined in the functional Hazard analysis." [Fault tree analysis. Wikipedia]
The shapes example "Fault tree analysis diagrams" was created using the ConceptDraw PRO diagramming and vector drawing software extended with the Fault Tree Analysis Diagrams solution from the Engineering area of ConceptDraw Solution Park.
FTA diagram symbols
FTA diagram symbols, voting gate, undeveloped event, transfer, priority AND gate, inhibit gate, house event, exclusive OR gate, event, conditional event, basic event, basic initiating fault, failure event, OR gate, AND gate,